Intel also discovered the power of the platform; by bundling a good CPU with a good chipset and wireless controller, three independent Intel products were transformed into a marketing powerhouse. The Centrino brand simplified notebook purchasing and quickly became a mark associated with a notebook you wanted to buy.
It took AMD a bit longer to get on the bandwagon, putting marketing first and worrying about architecture last. We had heard rumors of a mobile-specific AMD microarchitecture, but nothing ever surfaced until now. AMD’s design team out of Massachusetts worked on the project, and today we’re finally able to tell you about it. The processor is called Griffin, and the platform is called Puma, both are codenames; AMD will undoubtedly come up with a phenomenal name for the final product (sorry we couldn’t resist).
When Intel started development on the first Centrino processor, Banias, it had to go back to the P6 for a starting point. The Pentium 4′s NetBurst architecture was hardly suitable and the design team was intimately familiar with the P6 core at the time. The end product hardly resembled a P6 and if you look at what the architecture evolved into today, you would be hard pressed to say it was similar at all to a Pentium III.
AMD didn’t make the misstep of a Pentium 4, it made a solid evolutionary step to K8 from K7. Griffin’s execution core and underlying architecture is based on the current generation 65nm K8 design, not Barcelona/Phenom. You can take everything you are looking forward to being in Phenom and throw it out the window, as AMD is starting from the same K8 core that launched in 2003.
By no means is it a bad starting point, but thankfully AMD did toss in some enhancements. Griffin gets a new North Bridge, a new memory controller, a power optimized Hyper Transport 3 interface and a 1MB L2 cache per core. Griffin will still be built on a 65nm process as AMD will have, at best, only begun its 45nm production by the time Griffin debuts.
Right off the bat you see a disparity between AMD’s approach and Intel’s approach; while the K8 is arguably a better starting point for a mobile-specific architecture than the P6, the K8 was heavily designed for servers and scaled down. But as we’ve seen, the K8 is quite power efficient, with 35W TDPs easy achievable for dual core versions, so the race isn’t over before it has started.
Griffin will go into production at the end of this year, and AMD is targeting availability in the first half to middle of 2008. Given the launch timeframe, much like Phenom, AMD won’t be competing with today’s Core 2 processors but rather tomorrow’s Penryn based notebooks. Penryn does have some mobile-specific power improvements that even Griffin does not, but the opposite is also true as you will soon see. AMD quoted a maximum TDP of 35W for dual core Griffin CPUs. AMD hopes that notebooks based on Griffin can offer beyond 5 hours of battery life, but do keep in mind that battery life will vary greatly based on OEM implementation.
Truly Independent Power Planes
While architecturally Griffin is no different than today’s Athlon X2s, it will draw noticeably less power in normal use. AMD is the first to announce the next step in multi-core power management: independent voltages and frequencies for each core. While Phenom splits the North Bridge and CPU cores into two separate voltage planes, Griffin goes one step further and puts each individual CPU core onto an independent voltage plane. The benefit is that not only can each core run at its own frequency, but it can also run at lower voltages giving you significant reductions in power consumption.
Dynamic power of a CPU can be determined by the following equation:
Power = ∝ * C * V^2 * F
Simply reducing the frequency of a processor (F) will result in a linear reduction in power consumption, but as you can see voltage (V) has an exponential relationship to power. Reducing both is ideal, and that’s exactly what Griffin does.
Each core can run at one of 8 frequency steps and five voltage levels, independently of one another. Deep and deeper sleep states are supported, however AMD is currently looking into the possibility of implementing a C6 sleep state similar to what Intel announced for mobile Penryn. AMD wouldn’t commit to whether or not we’d see a C6 state in Griffin, leading us to believe that it simply wasn’t implemented at the time of Intel’s Penryn announcements and there may not be enough time to add it in before launch.
New Memory Controller
Although the underlying architecture of Griffin is K8 based, the memory controller takes a lot of cues from Barcelona/Phenom. There’s a new DRAM prefetcher, similar but not identical to what will be in Phenom, but many of the efficiency improvements in the new desktop core will make their way to Griffin as well. Taken from our Barcelona architecture article:
“One strength of Intel’s FB-DIMM architecture used in Xeon servers is that you can execute read and write requests to the AMB simultaneously. With standard DDR2 memory, you can do one or the other, and there’s a penalty for switching between the two types of operations. If you have a fairly random mixture of reads and writes you can waste a lot of time switching between the two rather than performing all of your reads sequentially then switching over to writes. The K8′s memory controller made some allowances for preferring reads over writes since they take less time, but in Barcelona the memory controller is far more intelligent.
Now, instead of executing writes as soon as they show up, writes are stored in a buffer and once the buffer reaches a preset threshold the controller bursts the writes sequentially. What this avoids is the costly read/write switch penalty, helping improve bandwidth efficiency and reduce latency.”
AMD did not make it clear whether Griffin also featured two independent 64-bit DDR2 memory controllers or a single 128-bit one. And, of course, as the memory controller is a part of the North Bridge it operates at a separate, lower voltage than the rest of the CPU cores.
Mobile Specific HT3
Much like Phenom, Griffin will support HyperTransport 3, offering more bandwidth between the CPU and the outside world. A major change to Griffin’s HT interface however is that it is highly power optimized.
By default, a Griffin CPU has two x16 HT3.0 links (one inbound and one outbound); depending on power and bandwidth requirements, those links can be dynamically scaled down to x8, x4, x2 or completely turned off. The inbound and outbound lanes can dynamically change independent of one another (e.g. inbound could be scaled to x8 while the outbound could be turned off). Each link width change requires a HT disconnect, meaning it can’t be done as frequently as a CPU frequency change, but the power savings should be substantial.
Better Thermal Control
Griffin adds better thermal control than its predecessor. The mobile K8 cores simply had a single on-die analog thermal diode that would report CPU temperature, while Griffin features two thermal sensors per core for more accurate thermal monitoring.
The current generation Turion CPUs communicate processor thermal data over the SMBUS, however an external thermal monitoring circuit is used requiring additional board real estate. Griffin supports an integrated SMBUS interface directly to the chipset, so there’s no extra chip required.
Griffin also allows monitoring of DRAM temperature (through an external temperature sensor placed near the DRAM modules) and based on pre-configured thermal limits, it can now throttle memory frequency if the modules get too hot.
Filed under: 1 Tagged: | AMD, ATI, News, Technology
